NVIDIA Nemotron 3 Ultra Tops Open Models in Agentic Register-Transfer Level Coding
NVIDIA introduced Nemotron 3 Ultra paired with the ACE-RTL agent framework, delivering a 97.1% average pass rate on the Comprehensive Verilog Design Problems benchmark. The 550B hybrid Mamba-Attention Mixture-of-Experts model reduces token usage by up to 71% per iteration compared to competing open models.
Impact: High
Why it matters
Hardware engineers and agent builders can leverage Nemotron 3 Ultra for long-context agentic code generation and debugging with significantly lower inference costs.
TL;DR
- 01NVIDIA Nemotron 3 Ultra achieves 97.1% pass rate on agentic RTL hardware benchmarks.
- 02Hybrid Mamba-Attention MoE architecture slashes token consumption by up to 71% per step.
- 03Iterative generate-test-reflect agent loops dramatically improve LLM performance on hardware design.
Key facts
- Total Parameters
- 550B
- Active Parameters
- 55B
- Context Window
- 1M tokens
- Pretraining Dataset
- 20T tokens
- Average Tokens/Iteration
- 6,629 (self-reported)
- CVDP Average Pass Rate
- 97.1% (self-reported)
Agentic RTL Development with Nemotron 3 Ultra
NVIDIA paired its Nemotron 3 Ultra model with the ACE-RTL agentic framework to automate complex Verilog and Register-Transfer Level (RTL) hardware design tasks. On the Comprehensive Verilog Design Problems (CVDP) benchmark, the combined pipeline achieved a 97.1% average pass rate across nine design categories, outperforming GLM 5.2 (92.1%) and Kimi K2.6 (95.2%).
Architecture and Token Efficiency
Nemotron 3 Ultra utilizes a 550B total parameter / 55B active parameter Mixture-of-Experts (MoE) Mamba-Attention hybrid design. By combining Mamba state-space layers with attention mechanisms, the model reduces the Key-Value (KV) cache footprint while sustaining a 1M token context window.
- Average token consumption:
6,629 tokensper iteration (vs.9,156for GLM 5.2 and22,579for Kimi K2.6). - Efficiency gain: Up to 71% fewer tokens per iteration compared to Kimi K2.6 and 28% fewer than GLM 5.2.
- Pass rate on debugging (cid016): Reached 100.0% when running inside the ACE-RTL agent loop.
Integration with EDA Pipelines
The model was trained using a synthetic data generation (SDG) pipeline sourced from public Verilog repositories and rubric-filtered hardware specifications. Its long-context efficiency makes it practical for integration into commercial Electronic Design Automation (EDA) suites from Cadence, Siemens, and Synopsys.
✓ When to use
- Building autonomous hardware engineering or Verilog coding agents
- Running long-context iterative LLM debugging loops with constraints on KV-cache memory
- Integrating AI code generation with traditional EDA simulation toolchains
✕ When NOT to use
- Standard web application development where general-purpose LLMs excel
- Low-latency real-time autocomplete where small dense models are required
What to do today
- Evaluate hybrid Mamba-Attention MoE models for context-heavy agentic feedback loops.
- Benchmark hardware synthesis or domain-specific code tasks using iterative generate-test-reflect loops.
Sources